This invention relates to systems for generating signals, and more particularly, to those systems which recover the color subcarrier signal and horizontal synchronization signal for digital video.
To convert an analog composite video signal into a digital video signal, the analog composite video signal must first be sampled by an analog-to-digital converter to create a digital composite video signal. The digital composite video signal is then converted by a digital video encoder to become digital component video. Techniques to convert an analog composite video signal into a digital component video signal are known in the art.
The digital component video signal is composed of a series of discrete, pixelized scan lines. Since there are a certain number of pixels per scan line and a certain number of scan lines per second encoding digital composite video a digital decoder requires a pixel clock. The pixel clock has frequency Fs that equals the number pixels per line times multiplied by the number of scan lines per second Fh.
One of the difficult aspects of the encoding process in a digital video encoder is chroma demodulation. The chroma portion of an analog video signal placed on a color subcarrier signal Fsc with a frequency of 3.579545 MHz. The hue (or color) value of pixel is determined by the phase difference of the color subcarrier signal during the pixel from a color burst reference signal. Television standards stipulate that the color subcarrier signal frequency be accurate to within +/xe2x88x9210 Hz. Inaccurate color subcarrier signal frequency precludes accurate reproduction of the color information. Therefore, a very accurate Fsc signal is required to demodulate chroma accurately.
Unfortunately, a digital video encoder must work with two separate signals with different frequencies: the pixel clock Fs and the color subcarrier signal Fsc. The standard pixel clock Fs and the color subcarrier signal Fsc do not have a simple integer multiple relationship. Moreover, since the input analog composite video signal is not likely to be stable (e.g., from VCR) there is likely to be a significant variation in the horizontal synchronization frequency Fh. If horizontal synchronization frequency Fh varies, while the pixel clock frequency stays fixed at Fs, some lines will have more or less pixels than the other lines and there will be inaccurate color demodulation.
The conventional solution for maintaining a proper relationship between the pixel clock Fs and the horizontal synchronization frequency Fh is to use a phase-locked loop (PLL) that generates a pixel clock signal that is synchronized with the input video signal. The problem with using a PLL to generate a pixel clock is that a PLL is usually implemented as an analog circuit. Thus, it is difficult to integrate an analog PLL into a digital video encoder design. Digital PLLs exist but they are hard to design.
If the problem of maintaining a proper relationship between the pixel clock Fs and the horizontal synchronization signal Fh is solved there still remains the problem of generating an accurate color subcarrier signal with frequency Fsc. The conventional solution for generating the color subcarrier signal has been to use a ratio counter.
The ratio between Fsc and Fs can be represented as the ratio p/q where p and q are two integers. Since Fs is greater than Fsc, whenever a pixel clock running at Fs completes one cycle, a clock generating Fsc would have completed p/q of one cycle. Using a ratio counter, a clock to generate Fsc can be obviated because for every clock pulse from the pixel clock the ratio counter can be incremented by p. During each clock cycle, the output of the counter expresses the phase of the color subcarrier signal as a fraction of one period of the pixel clock""s frequency, Fsc. Thus, the contents of the counter can be used as an index to a look-up table containing the amplitude of a sine wave for all possible values that can be stored in the counter. Using the look-up table, the phase can be translated to a corresponding amplitude.
A problem with generating the color subcarrier indirectly from a pixel clock is that the accuracy of the color subcarrier is very hard to control because the pixel clock is locked to the horizontal synchronization signal Fh that may vary by +/xe2x88x928%. Additionally, many errors can exist in different parts of the horizontal timing recovery and clock generation circuits that also affect the accuracy of color subcarrier Fsc. For example, in a conventional design, the look-up table for a phase-to-amplitude translator requires at least 2048 entries and still carries up to +/xe2x88x920.08% error that results in additional subcarrier phase error. Television standards stipulate that the color subcarrier frequency be accurate to within +/xe2x88x9210 Hz. Inaccurate subcarrier frequency precludes accurate reproduction of the color information.
Thus, it would be highly desirable to reproduce color more accurately and with circuitry less complicated than the mixed digital/analog PLL method.
An embodiment of the present invention provides a signal generator for generating a signal with a predetermined frequency. The signal generator includes a first comparator for generating a first error signal and a second comparator for generating a second error signal. The first and second comparators are coupled to an oscillator configured to receive the first and second error signals and generate the signal having a predetermined frequency.
Another embodiment of the present invention provides a signal generator for generating a signal with a predetermined frequency. The signal generator includes a counter for generating a first count, Q_last. The counter is coupled to a ratio counter which generates a signal having a value less than or equal to Q_last. The contents of the ratio counter represent the phase of the signal having a predetermined frequency. The ratio counter outputs the signal having a predetermined frequency.